module register #(
    parameter MEM_WIDTH = 16,
    parameter REG_NUM = 3
) (
    output [MEM_WIDTH-1:0] SR1_OUT,SR2_OUT,
    input [REG_NUM-1:0] SR1,SR2,
    input [REG_NUM-1:0] DR,
    input [MEM_WIDTH-1:0] DR_IN,
    input LD,//LD =1 write able
    input CLK
);
localparam MEM_DEPTH = 1<<REG_NUM;
    reg [MEM_WIDTH-1:0] reg_file [MEM_DEPTH-1:0];

     assign SR1_OUT = reg_file [SR1];
     assign SR2_OUT = reg_file [SR2];

    always @(posedge CLK) begin
        if (LD == 1'b1) begin
            reg_file [DR] <= DR_IN;
        end else begin
            reg_file [DR] <= reg_file [DR];
        end
    end
endmodule